Synchronizing system in time-division multiplex code modulation system



Nov. 20, 1962 HISASHI KANEKO 3,065,302

SYNCHRONIZING SYSTEM IN TIME-DIVISION MULTIPLEX CODE. MODULATION SYSTEMFiled Aug. 19, 1960 2 Sheets-Sheet 1 Hal [L i 1 GAT/lglg I I 3 w PULS r46 1 2 CH2 1 SIGNAL I SEPARATOR 1 956005 1 C'Hlbrl) i L CLOCK SYNC SYNCPULSE CHANNEL DECODER 5v ERROR PULSE F /6. 2a SYNC SYNC SYNC SYNC SYNCPULSE PULSE PULSE PULSE PUL E (n-7)CH ("n-11C (71-1)CH V I I l I l I I lI I l \:H|: I::\::\:H\:l::ll::-.l:| :|\|:l::||::LLL

k 1 Blair 2 DIGIT M DIGIB I "n CHANNELS mD/GITS PER CHANNEL FIG. 2b

mDlG/TS a T I I In I \:\l\:l::\::l:lll: l::lI::l|||-LLL SYNC CH1 CH2CH.(n-I) SYNC CHANNEL CHANNEL INVENTOR. HKANEKO AGENT MULTIPLEX C(DDEMOEULATZQN SYSTEM Hisashi Kaneiro, Tokyo, Japan, assi nor to NipponElectric Company, Limited, Tokyo, Japan, a corporation of Japan FiledAug. 1% will Ser. No. 50,623 Claims priority, application .lapan Nov.15, 1953 2 Qlaims. (til. l79---l5) This application is acontinuation-in-part of applicants original application, Serial Number842,897, filed September 28, 1959, and assigned to the same assignee,now abandoned.

This invention relates to a time-division multiplex system employingpulse code modulation and in particular to an improved method ofsynchronizing the multiplexed received signals with the multiplexedtransmitted signals.

An object of the invention is to devise a pulse code modulation systemin which the synchronizing pulse is of the same general type as thecoded pulses of the speech channels.

Another object of the invention is to devise a pulse code modulationsystem in which the number of digits in the synchronizing signal is thesame as the number of digits in a signal representing a quantized levelof the transmitted signal. A digit is identified as' a pulse or theabsence of a pulse.

Another object of the invention is to decrease the recovery time whichis necessary for restoring synchronism at the receiving terminal.

The above-mentioned and other features and objects of this inventionwill become apparent by reference to the following description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a time-division multiplex codemodulation receiving terminal equipment with special reference to thesynchronizing circuits;

FIGS. 2(a) and (b) are illustrative of two types of channel multiplexingwhich may be used with the synchronizing circuits of the invention;

FIG. 3 is a schematic diagram of a time-division multiplex codemodulation receiving terminal equipment which is identical with thatshown in FIG. 1 and illustrates the synchronizing circuits in greaterdetail; and

FIG. 4 is a block diagram of a code pattern generator.

In a time-division multiplex pulse modulation system in general, it isrequired that the sampling time for each channel be synchronized at boththe transmitting and receiving ends for channel selection at thereceiving end. To meet this requirement, a pulse sequence of one channelhas been used as synchronizing pulses, namely, such one channel has beenused as a synchronizing channel. In order to discriminate and separate apulse sequence of this synchronizing channel from pulse sequences ofother channels which may be the speech channels, it has ordinarily beennecessary to use as the synchronizing pulses such pulses that have alarger amplitude, a greater width, or a different shape, such as twinpulses.

In a time-division multiplex pulse code modulation system, it is notsuitable to differentiate the pulses of the synchronizing channel fromthose of the speech channels by the difference in pulse shape whenvarious factors such as pulse shaping in repeating, construction ofequipment, transmission frequency band, signal-to-noise ratio, and soforth are taken into consideration. There is, however, a known methodwhich employs a form of hunting circuit. With this method, synchronizingpulses of the same shape as the speech channel pulses have been used. Bymaking the synchronizing pulses alternately on and oil a synchronizingfrequency which is one-half that of the usual 3,lld5,32 Patented Nov.20, l92

sampling frequency (for example 4 kc. in place of 8 kc.) is obtained.The 4 kc. component is selected by a narrow bandpass filter at thereceiving end and caused to operate a relay whereby any collapse insynchronism is restored. Such method is described, for example, in J. M.Manleys paper entitled Synchronization for the PCM Receiver, BellLaboratories Record, February 1959, page 62. The advantages that areobtained by using PCM signals in the presence of low signal-to-noiseratio may also be obtained when using the pulses of the same shape forsynchronizing purposes.

Such a hunting system as just referred to, however, has defects in thatin case of collapse in synchronism, the recovering characteristics arepoor because of the low pass filters or bandpass filters which areemployed in this system in order to monitor the synchronizing channelsignal, and hence result in slow response of recovery. Furthermore, theconstruction of the circuits is complex.

ecording to the synchronizing system of the present invention thesynchronizing pulses are of the same shape as other channel pulses andthe synchronizing channel is selected by a simple logical circuitinstead of a complex circuit as described in the above-cited reference.The restoration to synchronism is performed by the use of a. coded pulsesequence of a channel which happened to be mis-selected in the event ofcollapse in synchronism. In short, the present invention is featured bythe rapidity and the reliability with which synchronism is restored andby the simplicity with which the synchronizing channel can beconstructed.

More particularly referring now to FIG. 1, which is a. schematic diagramof a time-division multiplex code modulation receiving terminalequipment according to this invention, multiplex pulse code sequencesare received at an input terminal 1, and the received input is appliedto both a logical circuit 2 and to a signal channel decoder 4 and asynchronizing channel decoder 5.

The receiving multiplex pulse code sequences may broadly be classifiedinto two types depending on the manner of multiplexing a plurality ofspeech channels and a synchronizing channel. FIG. 2 shows two typicaltypes in which n1 speech channels and one synchronizing channel aremultiplexed by an m-digit code. In one of them, shown in FIG. 2(a),coded pulses of the synchronizing channel and of the n-l speech channelsare interlaced in succession at n pulse intervals. In the other typeshown in FIG. 2(1)) each m-digit coded pulses of the synchronizingchannel and of the n-1 speech channels are arranged in succession.

In the case of the multiplex pulse code sequence shown in FIG. 2(a), themultiplex pulse code sequences applied to the signal channel decoder 4are first divided therein into individual speech channels by means ofchannelseparating or gating pulses supplied thereto from a channelseparator 3 and then each series of the separated coded pulses isdecoded also in the signal channel decoder 4. In the case of themultiplex pulse code sequences shown in FIG. 2( b), on the other hand,the applied multiplex pulse code sequences are first decoded at thesignal channel decoder 4 and then the decoded multiplex pulse sequencesare also divided therein into individual speech channel signals by meansof the gating pulses supplied thereto from the channel separator 3.Thus, decoded signals of the respective speech channels are obtained, ineither case, at output terminals 6 which correspond to the speechchannels, respectively.

The channel separator 3 in its turn is operated by a trigger signal orclock pulse given thereto from the logical circuit 2. A well'known ringcounter, as described by A. E. Johanson in the Bell Laboratories Recordfor lanuary 1949, on page 10, for example, is used for the channelseparator 3 wherein pulses are successively obtained at n outputterminals connected to both the signal channel decoder 4 and thesynchronizing channel decoder 5 The synchronizing channel decoder 5 isanother logical circuit which constitutes a decoder for thesynchronizing channel and confirms the existence of predeterminedsynchronizing pulses in the received multiplex pulse code sequencesapplied thereto. In case the signal pulse code of the applied multiplexpulse code sequences is different from the predetermined synchronizingpulse code, the synchronizing channel decoder 5 produces an error pulse,which is sent therefrom to the logical circuit 2.

The logical circuit 2. creates a series of clock pulses from themultiplex pulse code sequences applied thereto, and inhibits a clockpulse when the error pulse is fed back from the synchronizing channeldecoder 5. It will, therefore, be understood that insofar as thesynchronism is maintained, the trigger signal is of a clock pulse form,each pulse occurring at the fundamental pulse repetition frequency ofthe speech and synchronizing channels of the received multiplex pulsecode sequences. This trigger signal causes, in its turn, stepping of thering counter of the channel separator 3 to maintain the normal channelseparating operation.

it will also be understood that when the synchronism has collapsed, anerror pulse or a sequence of signals indicating the collapse is producedat the synchronizing channel decoder 5. This decoder 5, wherein anExclusive OR circuit is used, selects the synchronizing channel by wayof obtaining the logical product of the supplied synchronizing channelgating pulse and the applied multiplex pulse code sequences, andproduces the error pulse only when the selected pulse sequences do notcoincide with the predetermined synchronizing code. An error pulse actsin the logical circuit 2 to inhibit a clock pulse. When a coded pulsesequence of a channel selected at the synchronizing channel decoder 5does not coincide with the synchronizing pulse code, one clock pulse tohe sent to the channel separator 3 will drop for each non-coincidence.The existence of an error pulse, or the non-existence of the clockpulse, will delay the counting of the ring counter of the channelseparator 3 for one pulse interval. Through succession of this procedureat every non-coincidence the normal condition will be restored when thesynchronizing pulse code is eventually selected.

The logical circuit 2 and the synchronizing channel decoder 5 will nowbe explained in greater detail with special reference to FIG. 3. Thelogical circuit 2 comprises a clock pulse selector 7, a delay unit 8,and an inhibitor circuit 9. The clock pulse selector 7 is, for example,composed of a narrow band-pass filter which selects the basebandfrequency component, namely the fundamental repetition frequencycomponent, from the applied multiplex pulse code sequences and of acircuit which converts the baseband sinusoidal wave into a series ofclock pulses of the same frequency. Bandwidth of the filter is chosen asnarrow as possible, compared with the baseband frequency or the centerfrequency of the filter. Such a selector is referred to in theabove-mentioned Johanson paper.

The delay unit 8 gives delay time of substantially one clock interval tothe error pulse to be sent to the inhibitor circuit 9 from thesynchronizing channel decoder 5. At the inhibitor circuit 9, therefore,the error pulse, if it exists, will inhibit the next clock pulse in theclock pulse sequence. The inhibitor circut 9 is a well-known logicalcircuit such as described by I. Millman and H. Taub in Pulse and DigitalCircuit, a book published by McGraw Hill, 1956, on page 402 et seq.

Thus, the logical circuit 2 gives to the channel separator 3 the triggersignal which substantially is the clock pulses in case no error pulse isproduced at the synchronizing channel decoder 5, while it gives to thechannel separator 3 no clock pulse with the resulting delay of the apd.plication of the gating pulses to the decoders 4 and 5 for one pulseinterval per each error pulse.

The synchronizing channel decoder 5 comprises two AND circuits it} and11, a code pattern generator 12, and an Exclusively OR circuit 13. TheAND circuit it selects, by means of the gating pulses sent from thesynchronizing channel of channel separator 3, a series of pulses fromthe applied multiplex pulse code sequences. The AND circuit 1 selectsthe number of clock pulses which is contained in the synchronizingchannel pulse time interval from the clock pulses which have passedthrough the inhibitor 9 and triggers the code pattern generator 12,which in turn generates a synchronizing code sequence which conforms tothe predetermined pulse code.

The code pattern generator is, as shown in FIG. 4, composed. of a ringcounter 14, a group of programing switches 15, and a logical OR circuit16, each of the switches being connected between the respective outputterminals of the ring counter 14 and input terminals of the OR circuit16. The output of the AND circuit 11 advances the ring counter 14 one byone. If the ring counter comprises six stages and if the programingswitches 15 are positioned as shown in FIG. 4, for example, thesynchronizing code sequence which is obtained at the output of the ORcircuit 16 is 011001.

The Exclusively OR circuit or a non-coincidence circuit 13, such, forexample, as described in the abovementioned Millman and T aubs book,page 411 compares the output of the AND circuit 10 and of the codepattern generator 12, and derives the error pulse only when the outputof the AND circuit ltl does not coincide with that of the code patterngenerator 12. This means that the error pulse is produced at the verymoment where the selected pulse sequence happens to differ from thepredetermined synchronizing code.

While the channels are separated at the receiving terminal exactly insynchronism, no error pulse is produced at the Exclusively OR circuit13. Therefore, the normal operation of the receiving terminal equipmentis continued in such a way that the clock pulses pass through theinhibitor circuit 9 and advance the ring counter of the channelseparator 3 one by one. When the synchronism collapses, error pulses areoccasionally produced at the Exclusive OR circuit 13 and inhibit thefollowing clock pulses and shift the rotation of, or stop the steppingof, the ring counter of the channel separator .3, by one bit for eacherror pulse. This is a kind of a hunting procedure which continues untilthe normal phase of the rotation of the ring counter of the channelseparator 3 is eventually restored.

in the synchronizing system of the present invention a circuit having along time response, such as a narrow bandpass filter, is not present.The circuit, on the contrary, is mostly constructed with a set oflogical circuits each of which is practically independent of recoverycharacteristics, such as time response and other probability properties.Therefore, the hunting procedure is initiated immediately after thediscovery of the collapse of synchronism at the Exclusively OR circuit13 by causing only one bit of time delay, namely, the minimum timeinterval for the hunting operation. As a result, any collapse of thesynchronism is very rapidly restored.

The synchronizing pulse sequence is a predetermined code sequence at thetransmitting and receiving ends. Whether or not the coded pulse of eachspeech channel becomes on or otf is subject to the signal given to thechannel, and shows probability distribution. Accordingly, the occurrenceof the error pulse at the Exclusive OR circuit also shows probabilitydistribution in case of collapse of synchronism. Although 2 codedsequences are available by using an m-digit binary code for thepredetermined synchronizing code, the rapidity of recovery of thecollapse of the synchronism will of course be increased by selecting forthe predetermined synchroguesses nizing code the code sequence that hasthe least occurrence probability among all 2 coded pulse sequences.

It will be noted here that, although a most fundamental circuitconstruction has been shown in the present embodiment, simplerconstructions may be adopted by changing the method of various logicaloperations, such as by Boolean algebra in accordance with known logicaltransformation procedures.

The present embodiment can be applied to signals of various code typesby annexing a code conversion circuit. It may be utilized for all typesof digital transmission as well.

As has been fully described, the present invention, by employing asimple logical circuit using a pulse sequence of the same general typeas the channel pulse sequences in a time-division multiplex codemodulation system, provides a synchronizing system superior both instability and synchronization recovery characteristics. It is of greatpractical value when applied to a communication system for deliveringinformation expressed in digital quantities such as are used intelephony, telemetering, or telecontrol equipment.

While I have described above the principles of my invention inconnection with specific apparatus, it is to be clearly understood thatthis description is made only Way of example and not as a limitation tothe scope of my invention as set forth in the objects thereof and in theaccompanying claims.

What is claimed is:

1. A synchronizing circuit arrangement for a time-division multiplexsystem employing pulse code modulation and including a plurality ofsignalling channels and a synchronizing channel, said channels having apredetermined repetition frequency, the pulse code of the synchronizingchannel having the same characteristics as the pulse codes representingthe signals of the signalling channels comprising: an input terminal forreceiving both the signalling code pulses of the signalling channels andthe synchronizing code pulses; a channel separator, having a pluralityof signal channel outputs and a synchronizing channel output, forproviding gating pulses; means connected to said input for generating atrain of clock pulses coincident with, and having a recurrent frequencyequal to, the fundamental repetition frequency component of the receivedWave; means coupling said clock pulse generating means and said channelseparator for triggering said channel separator with said clock pulses;means connected to said coupling means for inhibiting said triggering; asynchronizing channel decoder connected to said synchronizing channeloutput and sal input and comprising means for generating the synchro.ing pulse code sequence and means responsive to gatii pulses on saidsynchronizing channel output for comparing t' e receiver pulse code withthe generated code and producing an error indication in the absence ofcoincidence; and delay means responsive to said error indication andconnected to said inhibiting means for preventing said channel separatorfrom receiving the next clock pulse.

2. A synchronizing circuit arrangement for a timedivision mu ti lexsystem employing pulse code modulation and including a plurality ofsignalling channels and a synchronizing channel, said channels having apredetermined repetition frequency, the pulse code of the synchronizingchannel having the same characteristics as the pulse codes representingthe signals of the signalling channels comprising: an input terminal forreceiving both the signalling code pulses of the signalling channels andthe synchronizing "ode pulses; a channel separator, having a piuralityof signal channel outputs and a synchronizing channel output, forproviding gating pulses; means connected to said input for generating atrain of clock pulses coincident with, and having a recurrent frequencyequal to, said repetition frequency; means coupling said clock pulsegenerating means and said channel separator for triggering said channelseparator With said clock pulses; a synchronizing channel decoder; asynchronizing code pattern generator in said decoder; a first AND gatein said decoder connected on its output to said code pattern generatorfor the triggering thereof to the next coded pulse in the synchronizingcode sequence and having an input connected to said coupling means andan input connected to said synchronizing channel output; a second ANDgate in said decoder having an input connected to said input terminaland an input connected to said synchronizing channel output; anexclusively C-R circuit connected to the outputs of said second AND gateand the output of said code pattern generator for producing an errorindication when the code signals received over said input terminal viasaid second AND gate do not coincide with the output of said patterngenerator; and means connected to said coupling means and responsive tosaid error indication for inhibiting the triggering of said channelseparator and said code pattern generator via said first AND gate by thenext clock pulse.

References Cited in the file of this patent UNITED STATES PATENTS2,949,503 Andrews et a1. Aug. 16, 1960

